** Error: (vsim-3033)

//SOURSE FILE

   module Monitor_test 
	(In_Add_Bit,In_Addr_L,In_Arry_L_Dat,Out_Arry_L_Dat);


     input        In_Add_Bit ;
     input  [3:0] In_Addr_L  ;
     input [15:0] In_Arry_L_Dat ;

     output[15:0] Out_Arry_L_Dat ;
 
    endmodule 
    
      //// TEST BENCH
  
  module Monitor_test_tb ; 
  
    	 
    reg          Add_Shift_Tb_R    ;
    reg    [3:0] Addr_L_Tb_R       ;
    reg   [15:0] Dat_L_Tb_R        ;
	wire  [15:0] Out_Dat_Tb_R      ; 

 	 
    wire          Add_Shift_Tb_R_Sig ;
    wire   [3:0]  Addr_L_Tb_R_Sig    ;
    wire  [15:0]  Dat_L_Tb_R_Sig     ;
	
   /// SOURSE CONECTION
  
	 Monitor_test DUT(.In_Add_Bit     (Add_Shift_Tb_R),  
	                  .In_Addr_L      (Addr_L_Tb_R)   ,
					  .In_Arry_L_Dat  (Dat_L_Tb_R)    ,
					  .Out_Arry_L_Dat (Out_Dat_Tb_R) );
							
			/// TEST BENCH VECTORS 				
							
	 Tb_Shift_Data DUT_Sh (.Out_Add_Bit_Sig   (Add_Shift_Tb_R_Sig) , 
	 	                   .Out_Addr_L_Sig      (Addr_L_Tb_R_Sig)    ,
						   .Out_Arry_L_Dat_Sig  (Dat_L_Tb_R_Sig)   ) ;
 endmodule
 
 
 
 /// TEST BENCH VECTORS

  module Tb_Shift_Data  (    Out_Add_Bit_Sig        , 
	                         Out_Addr_L_Sig         ,
							 Out_Arry_L_Dat_Sig  )  ;
							                      
	
	 
	  output          Out_Add_Bit_Sig     ;
      output [3:0]    Out_Addr_L_Sig      ;
	  output [15:0]   Out_Arry_L_Dat_Sig  ;
	   
	initial			 
		begin
	     Out_Add_Bit_Sig    = 1;
		 Out_Addr_L_Sig     = 4'h3;
		 Out_Arry_L_Dat_Sig = 16'h01;
		 #50;
		end
  endmodule