verilog clock question

I made a program that creates a clock, but during the simulation in the modelsim, the input signals are not displayed. Why?

 input MyInput;
 output Myoutput;
  assign MyInput=Myoutput;
  
   reg clk;
   initial begin clk = 1'b0;
   forever #2000000  clk = !clk;
   end
   

   reg clk1;
   initial begin clk1 = 1'b0;
   forever #10  clk1 = !clk1;
   
   
   
   end
 endmodule